Method of improving static refresh

ABSTRACT

A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductormemory devices and, more particularly to a structure having improvedstatic refresh properties in dynamic random access memory devices and amethod of making it.

[0003] 2. Description of the Related Art

[0004] Metal oxide semiconductor (MOS) structures are basic electronicdevices used in many integrated circuits. One such structure is themetal oxide semiconductor field effect transistor (MOSFET), which istypically formed in a semiconductor substrate by providing a gatestructure over the substrate to define a channel region, and by formingsource and drain regions on opposing sides of the channel region.

[0005] To keep pace with the current trend toward maximizing the numberof circuit devices contained in a single chip, integrated circuitdesigners continue to design integrated circuit devices with smaller andsmaller feature sizes. For example, not too long ago it was not uncommonto have MOSFET devices (including CMOS devices) having channel lengthsof 2 microns or more. The current state of the art for production MOSFETdevices includes channel lengths of less than a ¼ micron.

[0006] As the channel lengths of MOSFET devices have been reduced,MOSFETS have become more susceptible to certain problems. One commonproblem is increased junction leakage, a condition affecting the refreshcharacteristics of a dynamic random access memory (DRAM) memory cell.DRAM is a specific category of random access memory (RAM) containing anarray of individual memory cells, where each cell includes a capacitorfor holding a charge and a transistor for accessing the charge held inthe capacitor. Due to junction leakage, the stored charge must bere-stored in the capacitor on a periodic basis through a process knownas refresh. Increased junction leakage leads to a premature depletion ofthe capacitor's stored charge, necessitating more frequent refreshcycles. Because resources are expended in refreshing the DRAM cells, thelonger the period between refresh cycles, the better. The term “pause”is often used to represent the amount of time that a DRAM cell, or groupof cells, can maintain their charge without undergoing a refreshoperation. That is, how long can the DRAM control circuitry pausebetween refresh operations and still maintain the stored state of theDRAM memory cell. It is desirable to extend the pause period of, andimprove the static refresh of, the DRAM.

[0007] A manufacturer may want to improve static refresh performance ofthe DRAM to provide customers with the capability to perform more memoryoperations (e.g., reads and writes) between refresh cycles. This reducesthe overhead required to utilize the DRAM. Moreover, a manufacturer maywant to improve static refresh performance to improve the operatingspecifications of the DRAM. For example, DRAMs typically have alow-power or standby specification requiring the DRAM to operate withina maximum current during a low-power mode. Since memory cells must berefreshed during the lower-power mode, reducing the frequency of therefresh operations will improve the DRAM's operational performance forthe low-power mode.

[0008]FIG. 1 illustrates a prior art MOSFET memory array device 5. Thedevice 5 and its fabrication method are described in U.S. Pat. No.5,534,449 (Dennison et al.), which is hereby incorporated by referencein its entirety. Briefly, the fabrication of the device 5 is initiatedby forming a gate structure 10 on a substrate 8. The substrate 8 istypically a bulk silicon substrate, which may have a doped well thereinin which transistors are formed. The gate structure 10 (referred to inthe '449 patent as a gate line) typically comprises a gate oxide 12, aconductive polysilicon layer 14, an overlying WSi_(x) layer 16, anoverlying novellus oxide layer 18 and a Si₃N₄ capping layer 20. Thecross sectional width of this prior art gate structure 10 is 0.40microns.

[0009] Once the gate structure 10 is formed, the device 5 is subjectedto oxidizing conditions. This process step is often referred to as a“re-ox” step or a thermal re-ox step. Oxidized sidewalls 22, 24 areformed on the gate structure 10, and oxide regions 26, 28 are formed onthe substrate, as a result of the re-ox step. Subsequent to the re-oxstep, a blanket phosphorous implant step is performed to form diffusionregions 30, 32. This blanket phosphorous implant is performed at anenergy level ranging from 30 Kev to 60 Kev with a dose ranging from7×10¹² ions/cm² to 1.5×10¹³ ions/cm² to provide an average dopantconcentration for the diffusion regions 30, 32 ranging from 1×10¹⁷ions/cm³ to 1×10¹⁹ ions/cm³. For the prior art device 5, this blanketphosphorous implant step is performed after the re-ox step to preventthe phosphorous from diffusing too far underneath the gate structure 10,which could cause transistor leakage problems.

[0010] The fabrication process of the device 5 typically includes theformation of oxide or nitride sidewall spacers 40, 42 on the sidewallsof the gate structure 10. Further processing may be performed asdescribed in the '449 patent. Although the MOSFET memory array device 5is a vast improvement over earlier memory array devices, it can stillbenefit from improved static refresh performance. Thus, it is stilldesirable to improve as much as possible the static refresh performanceof the memory device.

SUMMARY OF THE INVENTION

[0011] The present invention provides a memory array device havingimproved static refresh over prior art memory array devices.

[0012] The above and other features and advantages of the invention areachieved by a double blanket ion implant method for forming diffusionregions in memory array devices, such as a MOSFET access device. Themethod provides a semiconductor substrate with a gate structure formedon its surface. Next, a first pair of diffusion regions are formed in aregion adjacent to the channel region by a first blanket ionimplantation process. The first blanket ion implantation process has afirst energy level and dose. The device is subjected to oxidizingconditions, which form oxidized sidewalls on the gate structure. Asecond blanket ion implantation process is conducted at the samelocation as the first ion implantation process adding additional dopantto the diffusion regions. The second blanket ion implantation processhas a second energy level and dose. The resultant diffusion regionsprovide the device with improved static refresh performance over priorart devices. In addition, the first and second energy levels and dosesare substantially lower than an energy level and dose used in a priorart single implantation process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of the preferredembodiments of the invention given below with reference to theaccompanying drawings in which:

[0014]FIG. 1 is a fragmentary vertical cross-sectional view of a priorart memory array device conventional diffusion regions;

[0015]FIG. 2 is a fragmentary vertical cross sectional view of anintegrated circuit memory array device formed in accordance with thepresent invention;

[0016]FIG. 3 is a fragmentary vertical cross sectional view of thedevice illustrated in FIG. 2 at an early stage of formation;

[0017]FIG. 4 is a fragmentary vertical cross sectional view of thedevice illustrated in FIG. 3 at a later stage of formation;

[0018]FIG. 5 is a fragmentary vertical cross sectional view of thedevice illustrated in FIG. 4 at a later stage of formation;

[0019]FIG. 6 is a fragmentary vertical cross sectional view of thedevice illustrated in FIG. 5 at a later stage of formation;

[0020]FIG. 7 is a fragmentary vertical cross sectional view of thedevice illustrated in FIG. 6 at a later stage of formation;

[0021]FIG. 8 is a graph illustrating the dopant concentration ofdiffusion regions within the devices illustrated in FIGS. 1 and 2;

[0022]FIGS. 9 and 10 are graphs illustrating the static refreshperformance of the devices illustrated in FIGS. 1 and 2; and

[0023]FIG. 11 is block diagram of a processor-based system including amemory device formed in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0024] The present invention will be described as set forth in thepreferred embodiments illustrated in FIGS. 2-7 and 11. Other embodimentsmay be utilized and structural or logical changes may be made withoutdeparting from the spirit or scope of the present invention. Like itemsare referred to by like reference numerals.

[0025]FIG. 2 illustrates a portion of an integrated circuit MOSFETmemory array device 105 constructed in accordance with the presentinvention. The device 105 is preferably used as an access device of aDRAM memory cell. As will be described with reference to FIGS. 3 to 7,the device 105 including diffusion regions 130, 132 is fabricated usingtwo blanket phosphorous ion implant steps sandwiched around aconventional re-ox step. Since two implant steps are performed,diffusion region 130 comprises two regions 130 a, 130 b having differentdopant concentrations. Similarly, diffusion region 132 comprises tworegions 132 a, 132 b having different dopant concentrations. Asdescribed with reference to FIGS. 9 and 10, the uniquely formeddiffusion regions 130, 132 provide the device 105 with improved staticrefresh performance over the prior device 5 (illustrated in FIG. 1).Since the method uses two separate blanket phosphorous ion implantsteps, it will be referred to hereinafter as a “double blanket ionimplant method.”

[0026] Hereinafter, the terms “wafer” and “substrate” are usedinterchangeably and are to be understood as includingsilicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology,doped and undoped semiconductors, epitaxial layers of silicon supportedby a base semiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a “wafer” or “substrate” in thefollowing description, previous process steps may have been utilized toform regions or junctions in the base semiconductor structure orfoundation.

[0027] In addition, no particular order is required for the method stepsdescribed below, with the exception of those logically requiring theresults of prior steps, for example formation of spacers 40, 42 adjacentto the sidewalls of the gate structure 10 logically requires the priorformation of the gate structure 10 and its sidewalls. Otherwise,enumerated steps are provided below in an exemplary order which may bealtered, for instance the several ion implant steps may be rearrangedusing masking and etching steps as is known in the art.

[0028]FIG. 3 shows the integrated circuit MOSFET memory array device 105in accordance with the present invention at an early stage of formation.A gate structure 110 is provided on the substrate 8 as is known in theart and described in the '449 patent to Dennison et al. The substrate 8is typically a bulk silicon substrate, which may have a doped well inwhich access transistors are to be formed. The gate structure 110comprises a gate oxide 12, a conductive polysilicon layer 14, anoverlying WSi_(x) layer 16, an overlying oxide layer 18 and a Si₃N₄capping layer 20. Unlike the gate structure 10 of the prior art device 5illustrated in FIG. 1, the cross sectional length of the gate structure110 may be substantially reduced. For example, the cross sectionallength of the gate structure 110 can be substantially reduced toapproximately 0.20 microns. An advantage of the present invention isthat the length of the gate structure 110 is reduced in comparison tothe prior art due to the unique fabrication processing of the presentinvention (described below).

[0029] Referring now to FIG. 4, diffusion regions 130 a, 132 a areformed in the substrate 8 adjacent the sidewalls of the gate structure110 and extend laterally away from the gate structure 110. It should benoted that a portion of the diffusion regions 130 a, 132 a diffusebeneath the gate structure 110. To create the diffusion regions 130 a,132 a, the substrate 8 undergoes a first blanket implant step. It isdesirable that an n-type be used, which makes the device 105 an NMOSdevice. It is desirable that the n-type dopant be phosphorous. However,it should be noted that other dopants can be used if so desired. Forexample, other n-type dopants such as arsenic or antimony could be used.If it were desirable for the device 105 to be a PMOS device, a p-typedopant such as boron, boron bifluoride (BF₂) or borane (B₂H₁₀) could beused. This first blanket phosphorous implant may be performed, forexample, at an energy level of approximately 15 Kev with a dose ofapproximately 2×10¹² ions/cm². It should be appreciated that any othersuitable dose and energy level can be used for this step. One exemplaryrange for the first blanket phosphorous implant may include an energylevel between approximately 5 Kev to 45 Kev with a dose of approximately1×10¹² ions/cm² to slightly less than 7×10¹² ions/cm².

[0030] It must be noted that this blanket phosphorous implant step isperformed prior to a subsequent re-ox step since the energy level anddose is substantially lower than the dose used in the prior art (i.e.,energy level ranging from 30 Kev to 60 Kev with a dose ranging from7×10¹² ions/cm² to 1.5×10¹³ ions/cm² to provide an average dopantconcentration for the diffusion regions 30, 32 ranging from 1×10¹⁷ions/cm³ to 1×10¹⁹ ions/cm³). Thus, the first blanket phosphorousimplant step can be performed prior to the re-ox step without having thephosphorous diffuse too far underneath the gate structure 110 andwithout causing subsequent transistor leakage problems.

[0031] Referring now to FIG. 5, a re-ox step is performed formingoxidized sidewalls 22, 24 on the gate structure 110 and oxide regions26, 28 on the substrate 8. It should be appreciated that anyconventional re-ox process can be performed at this point, such as athermal re-ox process or a source/drain thermal re-ox process. Referringto FIG. 6, diffusion regions 130 b, 132 b are formed in the substrate 8at the same location as diffusion regions 130 a, 132 b. To create thesecond diffusion regions 130 b, 132 b, the substrate 8 undergoes asecond blanket implant step. As with the first blanket implant step, itis desirable that the dopant used is phosphorous. However, it should benoted that other dopants can be used if so desired, particularly if adifferent conductivity type of the device 105 is desired. This secondblanket phosphorous implant may be performed at an energy level ofapproximately 20 Kev with a dose of approximately 4×10¹² ions/cm². Itshould be appreciated that any other suitable dose and energy level canbe used for this step. One exemplary range for the second blanketphosphorous implant may include an energy level between approximately 5Kev to 60 Kev with a dose of approximately 1×10¹² ions/cm² to 1×10¹³ions/cm².

[0032] The oxidized sidewalls 22, 24 on the gate structure 110 preventthe second implant from diffusing underneath the gate structure 110,which helps in the formation of the individual diffusion regions 130 a,130 b, 132 a, 132 b. The two diffusion regions 130 a, 130 b combine toform one diffusion region 130. The resultant diffusion region 130 willhave two different dopant concentrations, one from region 130 a and onefrom region 130 b. There will be a smooth transition between the dopantconcentrations of the two regions 130 a, 130 b. Similarly, the twodiffusion regions 132 a, 132 b combine to form one diffusion region 132.The resultant diffusion region 132 will have two different dopantconcentrations, one from region 132 a and one from region 132 b. Therewill be a smooth transition between the dopant concentrations of the tworegions 132 a, 132 b. As will be discussed below, these uniquely formeddiffusion regions 130, 132 allow the device 105 to have substantiallybetter static refresh performance in comparison to the prior art device5 (FIG. 1).

[0033] Referring to FIG. 7, oxide or nitride sidewall spacers 40, 42 maybe formed on the sidewalls of the gate structure 110 (as described inthe '449 patent or by any other known method). In addition, furtherprocessing may be performed to form a memory cell as described in the'449 patent. It can be seen that the device 105 has two diffusionregions 130, 132, each having a pair of diffusion regions 130 a, 130 b,132 a, 132 b, respectively.

[0034]FIG. 8 illustrates an exemplary phosphorous concentration 150 ofthe second diffusion region 132 with respect to its length (illustratedby arrow X). It should be noted that the first diffusion region 130would have a similar concentration, but in a direction opposite thedirection indicated by arrow X. An exemplary phosphorous concentration152 of the prior art device is also illustrated. From the curves 150,152 it can be seen how the second diffusion region 132 has a more gradedconcentration of phosphorous than the prior art diffusion regions (e.g.,region 32 in FIG. 1). By more graded, we mean that the net dopingconcentration versus distance changes gradually. By contrast, as shownby curve 152, the diffusion region 32 (FIG. 1) of the prior art devicehas an abrupt change in concentration of phosphorous versus distance.That is, the net doping concentration of the prior art curve 152undergoes a steep change with respect to distance. With a graded dopantconcentration of the diffusion regions, the resistance to current flowis less than the diffusion regions of the prior art. Although theinvention is not to be bound to any specific theory, it is believed thatthe more graded concentration of the present invention improves thestatic refresh of the device 105 by improving the junction at thestorage node of the DRAM memory cell.

[0035] Referring again to FIG. 7, it can be seen that the two diffusionregions 130, 132 slightly diffuse below the gate structure 110. That is,there is a first region 140 of the first diffusion region 130 thatresides underneath a portion of the gate structure 110. Similarly, thereis a second region 142 of the second diffusion region 132 that residesunderneath a portion of the gate structure 110. These regions 140, 142,which can be referred to as “overlap” regions, make the device 105 morerobust to reliability stressing. That is, the overlap regions 140, 142are less likely to degrade when high voltage is applied to the device,such as the types of voltages applied during manufacturing stresstesting. These regions 140, 142, which are not present in the prior artdevice 5 (FIG. 1), are formed by the first blanket phosphorous implantstep (FIG. 4). That is, by having the first blanket phosphorous implantstep (FIG. 4) prior to the re-ox step (FIG. 5) some dopant can diffuseunderneath the gate structure 110 forming region 140, 142 and causingthe device 105 to have the above-mentioned robustness. This is anotherbenefit of the present invention.

[0036] A standard measure of refresh performance is known as a “time toun-repairable calculation.” The term “repair” is sometimes used toindicate that a memory cell or memory bit has been repaired byelectrical replacement with a redundant element. The terms “un repaired”or “un-repairable” are often used to indicate that the number of failingbits exceeds the capability of repair by redundant elements. In the timeto un-repairable test, data is written into the bits of memory cells inthe DRAM array. Measurements are taken to determine when a predeterminednumber of bits have lost their charge and within what time. The time ittakes for the bits to lose their charge is commonly referred to as the“time to un-repairable” (TTUR).

[0037] Referring now to FIGS. 1, 2 and 9. The inventors ran experimentsto compare TTUR results using the prior art device 5 (FIG. 1) with theresults using the device 105 (FIG. 2) constructed in accordance with thepresent invention. FIG. 9 illustrates results from TTUR tests based onfinding 100 bits that have lost their charge. The y-axis indicates theprobability that 100 bits have lost their charge. The x-axis indicatesthe time when the charge was lost (and when a refresh operation becamenecessary). The first set of data 160 illustrates the results using thedevice 105 of the present invention. The second set of data 162illustrates the results using the device 5 of the prior art. From thedata 160, 162, it can be seen that 100 bits lost their charge (with 50%probability, i.e., 0.5 on the y-axis) using the prior art device 5 atapproximately 120 milliseconds, while 100 bits lost their charge usingthe device 105 at approximately 210 milliseconds. That is, there isalmost a 90 millisecond improvement in the device 105 constructed inaccordance with the present invention. It is believed that thisimprovement is due to the uniquely formed diffusion regions 130, 132 ofthe device 105.

[0038] Referring now to FIGS. 1, 2 and 10. FIG. 10 illustrates resultsfrom TTUR tests based on finding 200 bits that have lost their charge.The y-axis indicates the probability that 200 bits have lost theircharge. The x-axis indicates the time when the charge was lost (and whena refresh operation became necessary). The first set of data 170illustrates the results using the device 105 while the second set ofdata 172 illustrates the results using the device 5. From the data 170,172, it can be seen that 200 bits lost their charge (with 50%probability, i.e., 0.5 on the y-axis) using the prior art device atapproximately 240 milliseconds, while 200 bits lost their charge usingthe device 105 at approximately 310 milliseconds. That is, there isalmost a 70 millisecond improvement.

[0039]FIG. 11 illustrates a block diagram of a processor based system200 utilizing a DRAM memory circuit 208 constructed in accordance withthe present invention. That is, the memory circuit 208 utilizes theMOSFET memory array device 105 (FIG. 2) constructed in accordance withthe present invention (FIGS. 3 to 7). The processor-based system 200 maybe a computer system, a process control system or any other systememploying a processor and associated memory. The system 200 includes acentral processing unit (CPU) 202, e.g., a microprocessor, thatcommunicates with the DRAM memory circuit 208 and an I/O device 204 overa bus 220. It must be noted that the bus 220 may be a series of busesand bridges commonly used in a processor-based system, but forconvenience purposes only, the bus 220 has been illustrated as a singlebus. A second I/O device 206 is illustrated, but is not necessary topractice the invention. The processor-based system 200 also includes aread-only memory (ROM) circuit 210 and may include peripheral devicessuch as a floppy disk drive 212 and a compact disk (CD) ROM drive 214that also communicates with the CPU 202 over the bus 220 as is wellknown in the art. It should be noted that the CPU 202 can be combined ona single chip with one or more DRAM memory circuits 208 and ROM circuits210.

[0040] While the invention has been described in detail in connectionwith the preferred embodiments known at the time, it should be readilyunderstood that the invention is not limited to such disclosedembodiments. Rather, the invention can be modified to incorporate anynumber of variations, alterations, substitutions or equivalentarrangements not heretofore described, but which are commensurate withthe spirit and scope of the invention. Accordingly, the invention is notto be seen as limited by the foregoing description, but is only limitedby the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a device to be used in amemory array, the device comprising a gate structure provided on asurface of a semiconductor substrate, said method comprising the stepsof: forming a first doping implant within the substrate to form firstand second diffusion regions underneath the surface of the substrate onopposite sides of the gate structure; forming a second doping implantwithin the substrate at locations of the first and second diffusionregions to add additional dopant to the first and second diffusionregions, wherein each diffusion region comprises a first portion havinga first dopant concentration and a second portion having a second dopantconcentration.
 2. The method of claim 1 wherein the dopant is selectedfrom the group consisting of phosphorous, arsenic and antimony.
 3. Themethod of claim 2 wherein the dopant is phosphorous.
 4. The method ofclaim 1 wherein said first doping implant step is performed at a firstenergy level and first dose and said second doping implant is performedat a second energy level and second dose.
 5. The method of claim 4wherein the first energy level is different from the second energylevel.
 6. The method of claim 4 wherein the first dose is different fromthe second dose.
 7. The method of claim 4 wherein the first energy levelis less than 30 Kev and the first dose is less than 7×10¹² ions/cm². 8.The method of claim 4 wherein the first energy level is within a rangeof 5 Kev to 45 Kev and the first dose is within a range of 1×10¹²ions/cm² to less than 7×10¹² ions/cm².
 9. The method of claim 4 whereinthe first energy level is approximately 15 Kev and the first dose isapproximately 2×10¹² ions/cm2.
 10. The method of claim 4 wherein thesecond energy level is less than 30 Kev and the second dose is less than1×10¹³ ions/cm².
 11. The method of claim 4 wherein the second energylevel is within a range of 5 Kev to 60 Kev and the second dose is withina range of 1×10¹² ions/cm² to 1×10¹³ ions/cm².
 12. The method of claim 4wherein the second energy level is approximately 20 Kev and the seconddose is approximately 4×10¹² ions/cm².
 13. The method of claim 1 whereinthe first dopant concentration is different from the second dopantconcentration.
 14. The method of claim 1, wherein said first and seconddoping implants are performed by blanket ion implanting process.
 15. Themethod of claim 14, wherein sidewalls of the gate structure are oxidizedprior to said second doping implant.
 16. The method of claim 15, whereinthe sidewalls of the gate structure are oxidized by e thermal re-oxprocess.
 17. A method of forming a metal oxide semiconductor fieldeffect transistor comprising the steps of: providing a gate structure ona surface of a semiconductor substrate; implanting a dopant within thesubstrate to form first and second diffusion regions underneath thesurface of the substrate; oxidizing sidewalls of the gate structure; andimplanting the dopant within the substrate at locations of the first andsecond diffusion regions to add additional dopant to the first andsecond diffusion regions, wherein each diffusion region comprises afirst portion having a first dopant concentration and a second portionhaving a second dopant concentration.
 18. A method of forming a deviceon a substrate, the device comprising a gate structure provided on asurface of the substrate, said method comprising the steps of:implanting a dopant at a first energy level and first dose into thesubstrate to form first and second diffusion regions underneath thesurface of the substrate on opposite sides of the gate structure; andimplanting the dopant at a second energy level and second dose into thesubstrate at locations of the first and second diffusion regions to addadditional dopant to the first and second diffusion regions, whereineach diffusion region comprises a first portion having a first dopantconcentration and a second portion having a second dopant concentration.19. The method of claim 18 wherein the dopant is selected from the groupconsisting of phosphorous, arsenic and antimony.
 20. The method of claim19 wherein the dopant is phosphorous.
 21. The method of claim 18 whereinthe first energy level is different from the second energy level. 22.The method of claim 18 wherein the first dose is different from thesecond dose.
 23. The method of claim 18 wherein the first energy levelis less than 30 Kev and the first dose is less than 7×10¹² ions/cm². 24.The method of claim 18 wherein the first energy level is within a rangeof 5 Kev to 45 Kev and the first dose is within a range of 1×10¹²ions/cm² to less than 7×10¹² ions/cm².
 25. The method of claim 18wherein the first energy level is approximately 15 Kev and the firstdose is approximately 2×10¹² ions/cm².
 26. The method of claim 18wherein the second energy level is less than 30 Kev and the second doseis less than 1×10¹³ ions/cm².
 27. The method of claim 18 wherein thesecond energy level is within a range of 5 Kev to 60 Kev and the seconddose is within a range of 1×10¹² ions/cm² to 1×10¹³ ions/cm².
 28. Themethod of claim 18 wherein the second energy level is approximately 20Kev and the second dose is approximately 4×10¹² ions/cm².
 29. The methodof claim 18 wherein the first dopant concentration is different from thesecond dopant concentration.
 30. The method of claim 18, wherein saidimplanting steps are performed by a blanket ion implanting process. 31.The method of claim 30, wherein sidewalls of the gate structure areoxidized prior to said second implanting step.
 32. The method of claim31, wherein the sidewalls of the gate structure are oxidized by athermal re-ox process.
 33. A method of forming a memory array device ona substrate, the device comprising a gate structure provided on asurface of the substrate, said method comprising the steps of: blanketion implanting a dopant at a first energy level and first dose into thesubstrate to form first and second diffusion regions underneath thesurface of the substrate on opposite sides of the gate structure;oxidizing sidewalls of the gate structure; and blanket ion implantingthe dopant at a second energy level and second dose into the substrateat locations of the first and second diffusion regions to add additionaldopant to the first and second diffusion regions, wherein each diffusionregion comprises a first portion having a first dopant concentration anda second portion having a second dopant concentration.
 34. The method ofclaim 33, wherein said oxidizing step is a thermal re-ox process.
 35. Anintegrated circuit semiconductor device comprising: a substrate having afirst surface; a gate structure formed on said first surface; and firstand second diffusion regions formed within said substrate on oppositesides of said gate structure, wherein each of said diffusion regionscomprise first and second portions respectively having first and seconddopant concentrations, which are different and cause each diffusionregion to have a graded dopant concentration.
 36. The device of claim 35wherein said first and second diffusion regions are doped withphosphorous.
 37. The device of claim 35 wherein said first diffusionregion is partially located underneath a first side wall of said gatestructure and said second diffusion region is partially locatedunderneath a second side wall of said gate structure.
 38. Aprocessor-based system comprising: a processor; and a memory circuitcoupled to said processor, said memory circuit comprising: a substratehaving a first surface; a gate structure formed on said first surface;and first and second diffusion regions formed within said substrate onopposite sides of said gate structure, wherein each of said diffusionregions comprise first and second portions respectively having first andsecond dopant concentrations, which are different and cause eachdiffusion region to have a graded dopant concentration.
 39. Aprocessor-based system comprising: a processor; and a memory circuitcoupled to said processor, said memory circuit being integrated on asame chip as said processor, said memory circuit comprising: a substratehaving a first surface; a gate structure formed on said first surface;and first and second diffusion regions formed within said substrate onopposite sides of said gate structure, wherein each of said diffusionregions comprise first and second portions respectively having first andsecond dopant concentrations, which are different and cause eachdiffusion region to have a graded dopant concentration.